MTV 2005 - Call for Papers

CALL FOR PAPERS

Overview -- Author Information -- Committees

Overview

THE PURPOSE of this workshop is to bring researchers and practitioners from the fields of verification and test together to exchange innovative ideas and to develop new methodologies to solve the difficult challenges in various processor and SOC design environments. In the past few years, some work has been done on exploiting techniques from test to solve problems in verification and vice versa. This workshop should provide the ideal environment for cross test and verification experiences and innovative solutions.

AREAS OF INTEREST include, but not limited to:

Validation of microprocessors and SOCs
Experiences on test and verification of high performance processors and SOCs
Test/Verification of multimedia processors
Performance testing
High-level test generation for functional verification
Emulation techniques
Silicon debugging
Formal techniques and their applications
Verification coverage
Test Generation at the transistor level
Equivalence checking of custom circuits at the transistor level
Circuit level verification
Switch-level circuit modeling
Timing validation techniques
Path analysis for verification or test
Design error models
Design error diagnosis
Design for Testability or Verifiability
Optimizing SAT procedures with applications to testing and formal verification

Author Information

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Authors are invited to email postscript or PDF versions of their papers, with author names, affiliation, addresses, telephone and fax numbers, e-mail address, and the person who will present the work if accepted. Authors of accepted papers can submit the full paper for inclusion in the Workshop proceeding published by IEEE.

Please email your papers to licwang@ece.ucsb.edu and/or veneris@eecg.toronto.edu

DEADLINES

Paper/panel submission: August 15, 2005
Notification of Acceptance: September 10, 2005
Final version: October 10, 2005

Panel and Tutorial: Proposals for panel sessions and tutorials are also invited. Please email the abstract of your proposals directly to the program chair before paper submission deadline.

Committees

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General Chair
Magdy S. Abadir (Freescale, USA) – M.Abadir@freescale.com

Program Chair
Li-C. Wang (UCSB, USA) – licwang@ece.ucsb.edu

Program Co-Chair
Andreas Veneris (Univ. of Toronto, Canada) – veneris@eecg.toronto.edu

ORGANIZING COMMITTEE

Finance
M. Ray Mercer (Texas A&M Univ)

Publication
Jennifer Dworak (Brown University)

Panel
Al Crouch (Inovys)

Publicity
Tao Feng (Cadence Design Systems)

Committee
Moshe Levinger (IBM - Israel)

PROGRAM COMMITTEE

Jacob Abraham (UT-Austin)
Miron Abramovici (DAFCA)
Tony Ambler (UT-Austin)
Jayanta Bhadra (Freescale)
Eyal Bin, (IBM – Haifa)
Shawn Blanton (CMU)
Melvin Breuer (USC)
Ken Butler (TI)
Yirng-An Chen (Synopsys)
K.-T. (Tim) Cheng (UCSB)
Nick Dutt (UCI)
Sujit Dey (UCSD)
Franco Fummi (Univ. di Verona)
Mike Garcia (Freescale)
Sandeep Gupta (USC)
Ian Harris (U. Mass.)
John Hayes (U. Michigan)
Eric Hennenhofer (Obsidian, Inc.)
Alan J. Hu (UBC, Canada)
T. M. Mak (Intel)
Anmol Mathur (Calypto)
Hillel Miller (Freescale)
Sankaran Menon (Intel)
Manish Pandey (Cadence)
Carl Pixley (Synopsys, Inc.)
Paolo Prinetto (Poli di Torino)
Alper Sen (Freescale)
C. J. Richard Shi (U. of Washington)
Nur Touba (UT-Austin)
Miroslav Velev (CMU)
T. W. Williams (Synopsys)
Cheng-Wen Wu (Tsing-Hua Univ.)
Paul R Zehr (Intel)
Yervant Zorian (VirageLogic)

For more information, visit us on the web at: http://mtv.ece.ucsb.edu/MTV/

The 6th International Workshop on Microprocessor Test and Verification - MTV 2005 is sponsored by the Institute of Electrical and Electronics Engineers (IEEE) Computer Society's Test Technology Technical Council (TTTC).